Since a MOSFET is a unipolar device, parasitic capacitances are the only limiting factors in switching transient. The charge balance principle lowers on-resistance per specific area and enables shrinking the chip size for the same RDS(ON) compared to standard MOSFET technology. Figure 1 shows the capacitances of a Super-Junction MOSFET and a standard planar MOSFET. The Coss of a standard MOSFET shows moderate linear change, but the Coss curve of a Super-Junction MOSFET is highly non-linear. The initial value of Coss of a Super-Junction MOSFET is much higher due to higher cell density but Coss decreases very rapidly around 50 V of drain-source voltage in the case of a Super-Junction MOSFET as shown in figure 1. These non-linear effects can cause voltage and current oscillation when Super-Junction MOSFETs are used as a switching device for PFC or DC-DC converters. Figure 2 shows a simplified schematic of a PFC circuit with both the power MOSFETs internal parasitics and also an external oscillation circuit which contains an external couple capacitance Cgd_ext. due to board layout contributions.

AEP3214 Why the gate oscillation when using super-junction MOSFETs Figure 1

Figure 1. Comparisons of Output Capacitance between a Planar MOSFET and a Super-Junction MOSFET

From a general perspective, there are several oscillation circuits that effect the switching behavior of the MOSFET. This includes internal oscillation circuits and also external oscillation circuits. In the PFC circuit within figure 2, L, Co and Dboost are the inductor, output capacitor and boost diode, respectively. Cgs, Cgd_int, Cds are parasitic capacitances of the power MOSFET. Ld1, Ls1, Lg1 is the drain, source and gate wire bonding and lead inductances of power MOSFET. Rg_int and Rg_ext are the internal gate resistor of the power MOSFET and the external gate driving resistor of the circuit. Cgd_ext is the parasitic gate-drain capacitance of the circuit. LD, LS and LG are the drain, the source and the gate copper trace stray inductances of the printed circuit board (PCB). Gate parasitic oscillation occurs in a resonant circuit by gate-drain capacitance, Cgd and gate lead inductance, Lg1 when the MOSFET is turned on and off.

 AEP3214 Why the gate oscillation when using super-junction MOSFETs Figure 2

Figure 2. Simplified schematic of PFC circuit with internal and external parasitics of Power MOSFET

 In a resonance condition (ωL = 1/ωC), an oscillation voltage much larger than the drive voltage is generated in the gate and source voltage. The voltage oscillation, due to resonance changes, is in proportion to the quality factor, Q(=ωL/R = 1/ωCR). During MOSFET turn-off, drain leg inductances (LD + Ld1), gate-drain capacitance, Cgd and the gate lead inductance Lg1 network create a gate oscillation voltage. If the gate resistor (RG-ext.+Rg_int.) is extremely small, Q becomes large. Furthermore, the voltage drop across LS and Ls1 stray source inductances generate oscillation in gate-source voltage, which can be represented by equation (1). The parasitic oscillation can cause gate-source breakdown, bad EMI, large switching losses, losing gate control and can even lead to MOSFET failures.

AEP3214 Why the gate oscillation when using super-junction MOSFETs Equation 1

Optimizing circuit design is very important in order to maximize the performance of Super-Junction MOSFETs while mitigating the negative effects.

Related Links 

View SuperFET® II/SuperFET® II Easy-Drive MOSFET Product Portfolio:
http://www.fairchildsemi.com/search/controller?searchText=superfet+ii&textBtn.x=0&textBtn.y=0

For more information, please visit application note:
AN-5232: New Generation Super-Junction MOSFETs, SuperFET® II
http://www.fairchildsemi.com/an/AN/AN-5232.pdf

For Power Factor Correction, Power Train Discrete – Device Power Loss and Analysis (online tool):
http://www.fairchildsemi.com/support/design-tools/power-train-discrete-device-power-loss-and-analysis/