During dynamic load conditions, a flyback converter may produce overshoots and dips on the output side. These overshoots and dips have a direct relationship with the output capacitors. Understanding this relationship can help improve the design.

Figure 1 shows a simplified equivalent circuit for the output capacitor.

AEP3094 Fairchild Intro to Flyback Converter Tools Part 4 Figure 1

Figure 1. Output capacitor

 RC is the parasitic resistance for the capacitor, LC is the parasitic inductance for the capacitor, and C is the capacitance of the capacitor itself. During dynamic load conditions, if the load current goes up suddenly, the slow response time of the converter means the extra amount of load current goes through the output capacitors. This results in a voltage drop on RC and LC., and that makes the output voltage on C dip below its normal value.

Figure 2 gives an analysis of these parameters.

AEP3094 Fairchild Intro to Flyback Converter Tools Part 4 Figure 2

Figure 2. Behavior during dynamic load conditions

The output load current changes from IO1 to IO2, and the output voltage changes from VO1 to VO2. The slew rate of the dynamic load current is (IO2-IO1) /∆t. The discharging current on the capacitor creates a voltage drop of V1 on the parasitic inductance LC. The faster the load current changes, the bigger the V1 is. V2 is the voltage drop generated on the parasitic resistance due to the discharging current on the capacitor. The shape of V2 is similar to the profile of the discharging current. V1 disappears when the load current reaches IO2. This causes the output voltage to go down a little. The amplitude of the recess of the voltage is V1. V4 is the voltage variation when the capacitor C discharges, due to the charge variation on the capacitor. V4 is similar to a sine waveform. The converter eventually reacts by changing its duty ratio to supply the total IO2 to load, and the output voltage then settles at VO2.

Figure 2 shows that LC and RC are two critical parameters to consider when selecting output capacitors. LC determines the initial output voltage dip V1. The voltage drop V2 on RC super-imposes on V1, causing the output voltage to drop even more. These factors need to be account during the design phase.

Figure 2 also shows that V4 is due to the fact that the capacitor is discharging. This makes it important to select an output capacitor with the right capacitance. If the capacitance of the output capacitor is too small, the output voltage will dip even more during dynamic load.

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