Based on recent system trends, improving efficiency is a critical goal and going with slow switching device just for better EMI is not sometimes worth the trade-off. Super-junction can increase efficiency in applications planar MOSFET technology cannot. Super-junction MOSFETs have significant reduction in the on-resistance and parasitic capacitance compared with conventional planar MOSFET technology. While the significant reduction of on-resistance and parasitic capacitance reduction helps to improve efficiency, it also generates fast switching transitions in voltage (dv/dt) and current (di/dt) that can create high-frequency noises and radiated EMI.
To drive fast-switching super-junction MOSFETs, it is necessary to understand the package and PCB layout parasitic on switching performance and PCB layout adjustments to use super-junction MOSFETs. 500-600 V breakdown Super-junction MOSFETs are mainly used. In these voltage ratings, the most popular packages are industry standard TO-220, TO-247, TO-3P, and TO-263. The impact of the package on performance is limited due to the fact that the internal gate and source bonding wire length are fixed. Only the length of the lead can be changed to reduce the source inductance of the package. Typical lead inductance of 10 nH, as shown in Figure 1(a), doesn’t look like much, but a turn-off current with di/dt=500 A / µs is easily possible with these MOSFETs! Given a di/dt that is 500A / µs, the voltage across a 10nH lead inductance is VIND = 5 V; while a turn-off di/dt of 1,000 A / µs with a 10nH lead inductance can induce a voltage of VIND = 10 V. Most applications and designs don’t consider this additional inductance induced voltage, but should.
This simple calculation shows that the total source inductance, wire bond and lead inductance of the package must be reduced to acceptable value. Another source of noise is layout parasitic. Two types are visible: parasitic inductance and parasitic capacitance. 1 cm of trace pitch has an inductance of 6-10 nH, which can be reduced by adding one layer on the topside of the PCB and a GND plane on the bottom side of the PCB. The other type is the parasitic capacitances. Figure 1(b) shows the principles of capacitive layout parasitics. The capacitance between one trace is immediately over the other trace or GND plane on the other side of the PCB. The second one is the capacitance built up between the device and the GND plane. Two parallel traces on both sides of PCB increase capacitance, but also reduce the inductance of the loop, resulting in less magnetic noise radiation. Consider these layout tips the next time a design requires a super-junction MOSFET.
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