Minimizing the parasitic inductance and capacitance for the device and printed circuit board (PCB) board are important considerations for reducing unwanted noise. To drive fast switching super-junction MOSFETs in different applications, it is necessary to understand both the influence of parasitics in the device and layout. There are many considerations to design the proper gate drive circuit for fast switching MOSFETs. There are just a few key guidelines to minimize the unwanted noise.

Under certain conditions, e.g. transient at input voltage or short-circuit conditions, high di/dt and dv/dt exposures to the MOSFET can lead to unusual switching behavior or damaged devices. Figure 1 shows oscillatory waveforms of the super-junction MOSFET in a PFC circuit during turn-off transient. Parasitic components in the devices and boards are certainly the main causes for the unwanted oscillation and noise. In such a case, increasing gate resistance value dampens down the peak drain-source voltage and prevents gate oscillation caused by the lead inductance and parasitic capacitances of the super-junction MOSFET. It also slows down the rate of rise of the voltage (dv/dt) and current (di/dt) during the turn-on and turn-off process. Adversely, the extra external gate resistance also affects the switching losses in MOSFETs. As operating switching frequency increases, controlling switching losses are important as devices must achieve the highest efficiency for the target application.

AEP3215 Do this in your next gate drive design when using super-junction MOSFETs Figure 1

Figure 1. Severe oscillation waveforms in PFC circuit using super-junction MOSFET

 Another important means of avoiding oscillation is minimizing the device and board inductances. The right configuration of the gate drive circuitry is important to operate the MOSFET while minimizing the unwanted noise. There are two types of gate drivers to consider. Figure 2(a) gate drive circuit is most popular for fast variable turn-on and turn-off. Although more simple to implement, the fast turn-off transient and the larger gate turn-off loop can still create high di/dt and high voltage drop across the source inductance (Ldi/dt) generates gate oscillation. This creates unwanted side effects, like high voltage or current spikes or poor EMI performance. Another fast turn-on and fast turn-off gate drive circuit is a PNP transistor turn-off gate drive circuit in Figure 2(b). This more effective configuration can minimize source inductance in a smaller gate drive loop and still achieve fast turn-off.

AEP3215 Do this in your next gate drive design when using super-junction MOSFETs Figure 2Figure 2. Gate Drive Circuitry and Layout

 To achieve balance, it is important to have optimized gate drive circuitry because a power MOSFET is a gate-controlled device. The following recommendations are important to achieve both high efficiency without voltage spikes and lower EMI with fast switching MOSFETs.

Layout Guideline Summary for Fast Super-Junction MOSFETs

  • To achieve the best performance of SJ MOSFETs, optimized layout is required.
  • Gate driver and Rg must be placed as close as possible to the MOSFET gate pin.
  • Separate POWER GND and GATE driver GND.
  • Minimize parasitic Cgd capacitance and source inductance on PCB.
  • For paralleling SJ MOSFETs, symmetrical layout is mandatory.
  • Slow down dv/dt, di/dt by increasing Rg or using a ferrite bead. 

Related Links:

For more information, please visit application note: AN-9005: Driving and Layout Design for Fast Switching Super-Junction MOSFETs
http://www.fairchildsemi.com/an/AN/AN-9005.pdf

For Power Factor Correction, Power Train Discrete – Device Power Loss and Analysis (online tool)
http://www.fairchildsemi.com/support/design-tools/power-train-discrete-device-power-loss-and-analysis/