With the demands of energy savings for power semiconductors and power modules, packaging plays a major role in the overall performance of the product. The traditional wire bonded approach is widely used across a variety of packages. It is an established, cost-effective, flexible process with proven assembly infrastructure. However, the wire bonded package requires a higher number of source wires, in order to lower RDS(ON) or increase power density, and increasing the number of source wires impacts productivity and material cost (Au wire).
To meet the demands for improved product performance, clip technology is the preferred interconnect. Copper clip offers several benefits. It significantly reduces the overall package resistance of the product, compared to Cu wire, Au wire or Al ribbon source interconnect. Table 1 shows the RDS(ON) improvement of a Cu clip vs. the use of Al or Cu wire interconnect for the PQFN 5×6 dual asymmetric using fill the paddle die size for the LS FET. The use of Cu wire increases the resistance by 63 percent whereas the Al wire will increase by 43%. In addition to package resistance reduction, the clip interconnect also reduces thermal resistance and package inductance. The clip-bonded products have a higher current rating capability and efficiency by combining the reduction of thermal/electrical resistance and package source inductance.
Table 1: Rds comparison between Cu wire, Al wire and Cu clip
The clip-bonded package has an option of adding a heatslug on top of the clip or using a thick clip for two-sided cooling as shown below. The Dual Cool™ package improves thermal performance by 20% when an external fin heatsink is attached with air flow (200 LPM).
From a packaging standpoint, the copper clip is more cost effective than Al wirebonding. As the thin clip in reel is implemented in volume manufacturing, the Cu clip will achieve lower cost comparable to that of Cu wirebonding.
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